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HM514265D Series HM51S4265D Series
262144-word x 16-bit Dynamic RAM
ADE-203-581A (Z) Rev. 1.0 Nov. 28, 1996 Description
The Hitachi HM51(S)4265D Series is a CMOS dynamic RAM organized 262,144-word x 16-bit. HM51(S)4265D Series has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4265D Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM51(S)4265D to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44pin plastic TSOPII. Internal refresh timer enables HM51S4265D Series self reflesh operation.
Features
* Single 5 V (5%) (HM51(S)4265D-5/6R) (10%) (HM51(S)4265D-6/7/8) * Access time: 50 ns/60 ns/70 ns/80 ns (max) * Power dissipation Active mode: 945 mW/945 mW/990 mW/825 mW/715 mW (max) Standby mode: 10.5 mW (max) (HM51(S)4265D-5/6R) 11 mW (max) (HM51(S)4265D-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4265DL-5/6R) 1.1 mW (max) (L-version) (HM51(S)4265DL-6/7/8) * EDO page mode capability * 512 refresh cycles : 8 ms 128 ms (L-version) * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * 2CAS-byte control * Battery backup operation (L-version) * Self refresh operation (HM51S4265D Series)
HM514265D Series, HM51S4265D Series
Ordering Information
Type No. HM514265DJ-5 HM514265DJ-6 HM514265DJ-6R HM514265DJ-7 HM514265DJ-8 HM514265DLJ-5 HM514265DLJ-6 HM514265DLJ-6R HM514265DLJ-7 HM514265DLJ-8 HM51S4265DJ-5 HM51S4265DJ-6 HM51S4265DJ-6R HM51S4265DJ-7 HM51S4265DJ-8 HM51S4265DLJ-5 HM51S4265DLJ-6 HM51S4265DLJ-6R HM51S4265DLJ-7 HM51S4265DLJ-8 HM514265DTT-5 HM514265DTT-6 HM514265DTT-6R HM514265DTT-7 HM514265DTT-8 HM514265DLTT-5 HM514265DLTT-6 HM514265DLTT-6R HM514265DLTT-7 HM514265DLTT-8 HM51S4265DTT-5 HM51S4265DTT-6 HM51S4265DTT-6R HM51S4265DTT-7 HM51S4265DTT-8 HM51S4265DLTT-5 HM51S4265DLTT-6 HM51S4265DLTT-6R HM51S4265DLTT-7 HM51S4265DLTT-8 Access time 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 50 ns 60 ns 60 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DB) Package 400-mil 40-pin plastic SOJ (CP-40D)
2
HM514265D Series, HM51S4265D Series
Pin Arrangement
HM514265DJ/DLJ Series HM51S4265DJ/DLJ Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
HM514265DTT/DLTT Series HM51S4265DTT/DLTT Series
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8
NC NC WE RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
(Top view)
(Top view)
Pin Description
Pin name A0 to A8 Function Address input -- Row/Refresh address -- Column address Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power supply Ground No connection A0 to A8 A0 to A8
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
3
HM514265D Series, HM51S4265D Series
Block Diagram
I/O4 buffer I/O5 buffer I/O6 buffer I/O7 buffer I/O11 buffer
I/O4
I/O3 I/O3 buffer
I/O2 I/O2 buffer
I/O1 I/O1 buffer
I/O0 I/O0 buffer
I/O15 I/O15 buffer
I/O14 I/O14 buffer
I/O13 I/O13 buffer
I/O12 I/O12 buffer
I/O11
I/O5
I/O10 I/O10 buffer I/O9 buffer I/O8 buffer I/O9
I/O6
I/O7
I/O8
Selector
Selector
Selector
Selector
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
256 k memory array Mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
Row driver
Row Row driver driver
Row driver
Row driver
Row Row driver driver
Row driver
256 k memory array mat
WE RAS
UCAS
Row Decoder & Peripheral Circuit
LCAS OE
Row driver
Row Row driver driver
Row driver
Row driver
Row Row driver driver
Row driver
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
I/O bus & column decoder
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
256 k memory array mat
Row address buffer RA0 to RA8
Column address buffer CA0 to CA8
Address A0 to A8
4
256 k memory array mat
HM514265D Series, HM51S4265D Series
Operation Mode
The HM51(S)4265D series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle (HM51S4265D) 8. EDO page mode read cycle 9. EDO page mode early write cycle 10. EDO page mode delayed write cycle 11. EDO page mode read-modify-write cycle
Inputs RAS H H L L L L L H to L LCAS H L L L L L H H L L L L L L L H to L H to L H to L H to L L UCAS H L L L L L H L H L H to L H to L H to L H to L L H L* L*
2 2
WE D H H L* L*
2 2
OE D L L D H L to H D D
Output Open Valid Valid Open Undefined Valid Open Open
Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4265D)
H to L D D
L D H L to H H
Valid Open Undefined Valid Open
EDO page mode read cycle EDO page mode early write cycle EDO page mode delayed write cycle EDO page mode read-modify-write cycle Read cycle (Output disabled)
H to L H
Notes: 1. H: High(inactive) L: Low(active) D: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
5
HM514265D Series, HM51S4265D Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC (HM51(S)4265D-5/6R) VCC (HM51(S)4265D-6/7/8) Input high voltage Input low voltage VIH VIL Min 0 4.75 4.5 2.4 -1.0 Typ 0 5.0 5.0 -- -- Max 0 5.25 5.5 6.5 0.8 Unit V V V V V Notes 2 1, 2 1, 2 1 1
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
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HM514265D Series, HM51S4265D Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4265D-5/6R) *5 (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *5
HM514265D, HM51S4265D -5 Parameter Operating current* *2 Standby current
1,
-6/6R
-7
-8 125 mA RAS cycling UCAS or LCAS cycling t RC = min 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z mA CMOS interface RAS, UCAS, LCAS, WE, OE V CC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS, WE, OE VCC - 0.2 V Dout = High-Z
Symbol Min Max Min I CC1 -- 160 --
Max Min Max Min Max Unit Test conditions 150 -- 140 --
I CC2
--
2
--
2
--
2
--
--
1
--
1
--
1
--
1
Standby current (L-version)
I CC2
--
200 --
200 --
200
--
200 A
RAS-only refresh current* 2 CAS-before-RAS refresh current*2 EDO page mode current* 1, * 3
I CC3 I CC6 I CC4
-- -- -- --
150 -- 150 -- 180 -- 300 --
140 -- 140 -- 180 -- 300 --
130 130 150 300
-- -- -- --
110 mA t RC = min 110 mA t RC = min 130 mA t HPC = min 300 A
Standby: CMOS interface
I CC10 Battery backup current* 4 (Standby with CBR refresh) (L-version)
Dout = High-Z CBR refresh: tRC = 250 s t RAS 1 s, UCAS, LCAS = VIL WE, OE = VIH -- 1 -- 1 -- 1 -- 1 mA CMOS interface, RAS, UCAS, LCAS 0.2 V, Dout = High-Z CMOS interface, RAS, UCAS, LCAS 0.2 V, Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable
Self-refresh mode current (HM51S4265D) Self-refresh mode current (HM51S4265DL) Input leakage current Output leakage current
I CC11
I CC11
--
200 --
200 --
200
--
200 A
I LI I LO
-10 10 -10 10
-10 -10
10 10
-10 10 -10 10
-10 10 -10 10
A A
7
HM514265D Series, HM51S4265D Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4265D-5/6R)*5 (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *5 (cont.)
HM514265D, HM51S4265D -5 Parameter -6/6R -7 -8 Test conditions High Iout = -2 mA Low Iout = 2 mA
Symbol Min Max Min 2.4 0 VCC 0.4 2.4 0
Max Min Max Min Max Unit VCC 0.4 2.4 0 VCC 0.4 2.4 0 VCC 0.4 V V
Output high voltage VOH Output low voltage VOL
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less within one EDO page cycle. 4. VIH VCC - 0.2 V, 0 VIL 0.2 V, Address can be changed once or less while RAS = VIL. 5. All the V CC pins should be supplied with the same voltage. And all the VSS pins should be supplied with the same voltage.
Capacitance (Ta = +25C, VCC = 5 V 5%) (HM51(S)4265D-5/6R) (Ta = +25C, VCC = 5 V 10%) (HM51(S)4265D-6/7/8)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4265D-5/6R)*1, *14, *15, *17, *18 (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4265D-6/7/8)*1, *14, *15, *17, *18
Test Conditions * * * * * Input rise and fall time : 2 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V* Output load : 1 TTL gate + CL (50 pF) (Including scope and jig)
8
HM514265D Series, HM51S4265D Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514265D, HM51S4265D -5 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Symbol Min t RC t RP t RAS t CAS t ASR 84 30 50 8 0 8 0 8 18 10 13 40 10 13 0 0 2 -- -- Max -- -- -6/-6R Min 104 40 Max -- -- -7 Min 124 50 Max -- -- -8 Min 144 60 Max -- -- Unit ns ns 27 28 Notes
10000 60 10000 10 -- -- -- -- 35 25 -- -- -- -- -- -- 50 8 128 0 10 0 10 20 15 15 48 10 15 0 0 2 -- --
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 8 128 0 10 0 13 20 15 18 58 10 18 0 0 2 -- --
10000 80 10000 15 -- -- -- -- 50 35 -- -- -- -- -- -- 50 8 128 0 10 0 15 20 15 20 68 10 20 0 0 2 -- --
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 8 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
Row address hold time t RAH Column address setup t ASC time Column address hold time RAS to column address delay time RAS hold time CAS hold time t CAH
19 19 8 9
RAS to CAS delay time t RCD t RAD t RSH t CSH
29 20
CAS to RAS precharge t CRP time OE to Din delay time CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) t ODD OE delay time from Din t DZO t DZC tT t REF t REF
7
9
HM514265D Series, HM51S4265D Series
Read Cycle
HM514265D, HM51S4265D -5 Parameter Access time from RAS Access time from CAS Access time from OE Read command setup time Symbol t RAC t CAC Min -- -- -- -- 0 0 0 25 13 -- -- 13 13 13 13 -- -- 5 5 50 15 25 Max 50 15 25 15 -- -- -- -- -- 13 13 -- -- -- -- 13 13 -- -- -- -- -- -6/-6R Min -- -- -- -- 0 0 0 30 18 -- -- 15 15 15 15 -- -- 5 5 60 15 30 Max 60 15 30 15 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- -7 Min -- -- -- -- 0 0 0 35 23 -- -- 18 18 18 20 -- -- 5 5 70 18 35 Max 70 20 35 20 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- -8 Min -- -- -- -- 0 0 0 40 28 -- -- 20 20 20 20 -- -- 5 5 80 20 40 Max 80 20 40 20 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 23 6, 25 6 6, 25 6 Notes 2, 3 3, 4, 13 3, 5, 13 3, 23 19 16, 20 16
Access time from address t AA t OAC t RCS
Read command hold time t RCH to CAS Read command hold time t RRH to RAS Column address to RAS lead time Column address to CAS lead time t RAL t CAL
Output buffer turn-off time t OFF1 Output buffer turn-off time t OFF2 to OE CAS to Din delay time RAS to Din delay time WE to Din delay time OE pulse width Turn-off to RAS Turn-off to WE Output data hold time Output data hold time from RAS t CDD t RDD t WDD t OEP t OFR t WEZ t OH t OHR
Read command hold time t RCHR from RAS Read command hold time t RCHC from CAS Read command hold time t RCHA from column address
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HM514265D Series, HM51S4265D Series
Write Cycle
HM514265D, HM51S4265D -5 Parameter Symbol Min 0 8 8 8 8 0 8 Max -- -- -- -- -- -- -- -6/-6R Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- -8 Min 0 15 10 15 15 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 21 11, 21 11, 21 10, 19 19
Write command setup time t WCS Write command hold time Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time t WCH
Write command pulse width t WP t RWL t CWL t DS t DH
Read-Modify-Write Cycle
HM514265D, HM51S4265D -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 109 65 30 42 13 Max -- -- -- -- -- -6/-6R Min 133 77 32 47 15 Max -- -- -- -- -- -7 Min 159 90 38 55 18 Max -- -- -- -- -- -8 Min 183 102 42 62 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 10 10 10
11
HM514265D Series, HM51S4265D Series
Refresh Cycle
HM514265D, HM51S4265D -5 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol Min t CSR t CHR t RPC t CPN 10 10 10 8 Max -- -- -- -- -6/-6R Min 10 10 10 10 Max -- -- -- -- -7 Min 10 10 10 13 Max -- -- -- -- -8 Min 10 10 10 15 Max -- -- -- -- Unit Notes ns ns ns ns 19 20 19 22
EDO Page Mode Cycle
HM514265D, HM51S4265D -5 Parameter EDO page mode cycle time Symbol Min t HPC 20 8 -- -- 30 5 8 5 30 Max -- -- -6/-6R Min 25 10 Max -- -- -7 Min 30 13 Max -- -- -8 Min 35 15 Max -- -- Unit Notes ns ns 12 3, 13, 17 24
EDO page mode CAS t CP precharge time EDO page mode RAS t RASC pulse width Access time from CAS t ACP precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge t RHCP t DOH t COL t COP t RCHP
100000 -- 28 -- -- -- -- -- -- 35 5 10 5 35
100000 -- 35 -- -- -- -- -- -- 40 5 13 5 40
100000 -- 40 -- -- -- -- -- -- 45 5 20 5 45
100000 ns 45 -- -- -- -- -- ns ns ns ns ns ns
26
12
HM514265D Series, HM51S4265D Series
EDO Page Mode Read-Modify-Write Cycle
HM514265D, HM51S4265D -5 Parameter EDO page mode readmodify-write cycle time EDO page mode readmodify-write cycle CAS precharge to WE delay time Symbol t HPCM t CPW Min 57 45 Max -- -- -6/-6R Min 66 52 Max -- -- -7 Min 77 60 Max -- -- -8 Min 86 67 Max -- -- Unit ns ns 10 Notes
Self Refresh Mode
HM51S4265D -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 90 -50 Max -- -- -- -6/-6R Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit Notes ns ns ns 21 30, 31, 32
Notes: 1. AC measurements assume t T = 2 ns, VIH = 3.0 V, VIL = 0.0 V 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD t CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
13
HM514265D Series, HM51S4265D Series
11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in EDO page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 20. t CRP , t CHR, t ACP, tRCH and t CPW are determined by the later rising edge of UCAS or LCAS. 21. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 22. t CPN and t CP are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 24. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 25. t OFF1 and t OFR are determined by the later rising edge of RAS or CAS. 26. t DOH defines the time at which the output level satisfies the output timing reference levels. Measured with the test conditions. 27. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 28. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 29. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min). 30. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS > 100 s, then RAS precharge time should use t RPS instead of tRP. 31. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 32. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 33. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 34. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
14
HM514265D Series, HM51S4265D Series
Notes concerning 2CAS control
1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS Delayed write UCAS Early write LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, fast page mode can be performed.
RAS
UCAS
LCAS t UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
15
HM514265D Series, HM51S4265D Series
Timing Waveforms*34
Read Cycle
t RC t RAS
RAS tT t RCD t RSH t CAS t CSH t RP t CRP
UCAS LCAS t RAD t ASR t RAH t ASC t RAL t CAH
Address
Row
Column t CAL t RCHR t RCHC t RCHA t OH t OHR t RCH t RRH t CAC t AA t OFR t OFF1 Dout t RAC t DZC t OAC High-Z t WDD t DZO t OEP t ODD t OFF2 t CDD t WEZ t RDD
t RCS
WE
Dout
Din
OE
16
HM514265D Series, HM51S4265D Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
t RP
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z
17
HM514265D Series, HM51S4265D Series
Delayed Write Cycle
t RC t RAS
t RP
RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RWL t RSH t CAS t CRP
Address
Row
, + * $
t RCS t WP WE t DS t DH Din High-Z Din t DZC t DZO t ODD t OEH Dout
Invalid Dout*
t OFF2
OE
*
* Do not enable Dout during delayed write cycle.
18
HM514265D Series, HM51S4265D Series
Read-Modify-Write Cycle
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
UCAS LCAS t ASR
t RAD t RAH t ASC tCAH
Address
Row t RCS
Column t CWD t AWD t CWL t RWL t WP
WE t RWD t RAC t DZC Din
High-Z
t AA t CAC t DS t DH
Din
Dout t OAC
Dout
t OFF2 t DZO OE t OEP t ODD
t OEH
19
HM514265D Series, HM51S4265D Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP tRPC tCRP
UCAS LCAS t ASR t RAH
Address
Row
Dout
High-Z
20
HM514265D Series, HM51S4265D Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS * t RP t RC t RAS * t RP
RAS tT t RPC t CPN t RPC t CHR t CPN t CSR t CHR t CRP t CSR

LCAS Address t OFF1 Dout High-Z
, ,
UCAS
> * Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514265D/DL).
21
HM514265D Series, HM51S4265D Series
EDO Page Mode Read Cycle (tHPC minimum cycle operation)
t RASC t RHCP t RP
RAS tT t CSH t RCD UCAS LCAS t ASR t RAD t RAH Address Row tASC t CAL t CAH Column 1 t CAL t ASC t CAH Column 2 t ASC t CAL t RAL t CAH Column 3 t RCHA t RCS WE t DZC t WEZ t CDD Din t CAC t RAC t AA High-Z t CAC t AA t ACP t DOH Dout t OAC t DZO OE t OFF2 Dout 1 t CAC t AA t ACP t DOH Dout 2 t OFR t RCHP t RCHC t RRH t RCH t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t OH t ODD t OHR
t OFF1 Dout 3
22
HM514265D Series, HM51S4265D Series
EDO Page Mode Read Cycle (High-Z control by WE and OE)
t RP
RAS
t RASC tT t CSH t CAS t RCS t RCHR t RCHC t RCHA tASR tRAH t ASC tCAH Row tDZC Column 1 tCAL High-Z t ASC t CAH
Column 2
t HPC t HPC tCAS t RCHP t RHCP t CP tCAS t RRH t RCH t t RAL RCHC t ASC t CAH
Column 3
t CP
t HPC t CAS
t CRP
t CP
UCAS LCAS
t RCH t RCS
WE
tASC
t CAH
Column 4
t WDD
Address
t CAL
t CAL
t CAL
tRDD tCDD
Din
tDZO
OE
tCOL
tCOP tODD
tOAC tCAC tAA tRAC
Dout
tACP tAA tCAC tWEZ tOFF2 tOAC Dout 2
tACP tACP tAA tCAC tDOH Dout 2
Dout 3
tAA tOFF2 tCAC tOAC Dout 4
tOFR tOHR tOFF2 tOFF1 tOH
Dout 1
23
HM514265D Series, HM51S4265D Series
EDO Page Mode Early Write Cycle (tHPC minimum cycle operation)
t RASC t RP
RAS tT t CSH t RCD UCAS LCAS t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t CAH
Address
Row
Column
Column
Column
t WCS
t WCH
t WCS
t WCH t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din
Din
Din
Dout
High-Z
24
HM514265D Series, HM51S4265D Series
EDO Page Mode Delayed Write Cycle
t RASC t RP
RAS tT t CSH tRCD UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
Address
Row
Column t CWL t WP
Column t CWL t WP t RWL
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
25
HM514265D Series, HM51S4265D Series
EDO Page Mode Read-Modify-Write Cycle
t RP
t RASC RAS t RCD tT
UCAS LCAS
t HPCM t CP t CAS t CAS t ACP t CAH t ASC t CAH t CAH t ASC t CP t CAS t CRP
t RAD t RAH t ASR t ASC
Address
Row
Column t AWD t CWD t RWD t CWL t WP t RCS
Column t AWD t CWD t CPW t CWL t WP
Column t CPW t AWD t RCS t CWD t CWL t RWL t WP
t RCS
WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 t OEH t DZC t CAC High-Z t AA t DS t DH t ACP t DZC High-Z t CAC t AA t OAC Dout t OFF2 t OEH t DS t DH
t DZC
Din
Din
Din
Din
t DZO
OE t ODD t OEP t OEP t ODD tOEP t ODD
26
HM514265D Series, HM51S4265D Series
EDO Page Mode Mix Cycle (1)*24
t RP RAS tT UCAS LCAS t WCS WE tASR Address Row t ASC tRAH tCAH t ASC t CAH Column 2 t CAL High-Z tODD OE t ACP tAA tOAC tCAC tDZO t ACP tAA tCAC t DOH Dout Dout 2
Dout 3
t RASC t CSH t CAS t WCH tCPW tAWD tASC t CAH Column 3 t CAL t DS t DH tWP tASC t CP t CAS t CP tCAS t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
Column 1 tCAL t DH Din 1
t DS
Din
Din 3 tWDD
tACP tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
tOFF2
27
HM514265D Series, HM51S4265D Series
EDO Page Mode Mix Cycle (2)*24
t RP RAS tT UCAS LCAS t RCS WE tASR Address Row t ASC tRAH tCAH t ASC t CAH Column 2 t DS
Din
t RASC t CSH t CAS t RCHR t RCH t WCS t WCH tCPW t ASC t CAH Column 3 t CAL t DS t DH t CP t CAS t CP tCAS tCWL tWP tASC t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
Column 1 tCAL High-Z
t CAL t DH Din 2
Din 3 tDZO tODD tDZO tWDD
tODD OE tAA tOAC tCAC tRAC tOFF2
t OAC tACP tAA tCAC
tACP tOFF2 tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
Dout
Dout 1
Dout 3
28
HM514265D Series, HM51S4265D Series
Self Refresh Cycle *30, 31, 32, 33
t RP
t RASS
t RPS
RAS tT t RPC t CPN t CRP t CHS t CSR

LCAS Address t OFF1 Dout High-Z 29
,
UCAS
HM514265D Series, HM51S4265D Series
Package Dimension
HM514265DJ/DLJ Series HM51S4265DJ/DLJ Series (CP-40D)
Unit: mm
25.80 26.16 Max 40 21 10.16 0.13 0.74
3.50 0.26
1
20
11.18 0.13
1.30 Max
0.25 0.80 + 0.17 -
0.43 0.10 0.41 0.08
1.27
9.40 0.25
0.10
Hitachi Code JEDEC Code EIAJ Code Weight
CP-40D -- SC-640 1.73 g
30
0.31 2.30 + 0.14 -
HM514265D Series, HM51S4265D Series
HM514265DTT/DLTT Series HM51S4265DTT/DLTT Series (TTP-44/40DB)
Unit: mm
44
18.41 18.81 Max 35 32
23
1 0.27 0.07 0.25 0.05
10 13 0.80 0.13 M 1.005 Max
22 0.80
10.16
11.76 0.20 0 - 5 0.50 0.10 0.68 31
1.20 Max
0.145 0.05 0.125 0.04
2.40
0.10
0.13 0.05
Hitachi Code JEDEC Code EIAJ Code Weight
TTP-44/40DB MO-133BA SC-504-8C 0.43 g
HM514265D Series, HM51S4265D Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
32
HM514265D Series, HM51S4265D Series
Revision Record
Rev. 0.0 1.0 Date May. 20, 1996 Nov. 28, 1996 Contents of Modification Initial issue Deletion of preliminary AC Characteristics Change of note 34 Addition of note 4 to Notes concerning 2CAS control Timing Waveforms Deletion of notes about undefined pins Drawn by Approved by H. Hisakawa S. Suzuki
33

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